Gain compensation based on a first gain factor and a second gain factor with time-varying compensation

ABSTRACT

An automatic gain control circuit has a gain determination circuit (B 2 ) which determines a first gain factor (g), and a first gain controller (B 3 ) which controls an amplitude of an input signal (S 1 ) with the first gain factor (g) to supply a gain controlled signal (S 3 ). A processing circuit (B 1 ; B 1 , B 11 ) with a predetermined limited dynamic range processes the gain controlled (S 3 ) to obtain an output signal (S 4 ; S 2 ). The automatic gain control circuit further comprises a compensation circuit (B 5 ) which determines a second gain factor (dg) based on the first gain factor (g) and input parameters (DL, TR, DV) which define a time variation of the second gain factor (dg), and a second gain controller (B 1 ; B 10 ) which receives the second gain factor (dg) to obtain a compensated output signal (S 2 ) that is substantially compensated for an amplitude change of the gain controlled signal (S 3 ) due to a change of the first gain factor (g).

The invention relates to a device comprising a processing circuit with apredetermined limited dynamic range and an automatic gain controlcircuit, a method of automatic gain control, and an audio apparatuscomprising such a device.

U.S. Pat. No. 5,389,927 discloses that automatic gain control (AGC) istypically used in a receiver to prevent saturation of one or more stageswhich saturation is caused by exceeding the dynamic range of a stage bya too large input signal. This prior art further discloses that applyingAGC techniques to digital receivers as well to control front end gainand digital gain is well known. The control of the front end gainovercomes the problem of insufficient dynamic range of the analog todigital converter (ADC) in digital receivers.

Further, U.S. Pat. No. 5,389,927 discloses that in such a digitalreceiver with a front end which supplies an analog signal with a leveldepending on the signal strength received at the antenna, the ADCconverts an analog input signal supplied by a front end into a digitalsignal which is a digital representation of the analog signal. Adetector detects the current signal amplitude of the digital signal andsupplies a control signal to an amplitude controller which controls theamplitude of the analog input signal in steps to obtain a controlledanalog signal which has an amplitude within the operating range of theADC.

It is an object of the invention to provide an automatic gain controlwhich produces at an amplitude change of a controlled input signal dueto an automatic gain control action, a signal amplitude of an outputsignal which better resembles the amplitude of the input signal.

To this end, a device comprises a processing circuit with apredetermined limited dynamic range, and an automatic gain controlcircuit comprising:

a gain determining circuit for determining a first gain factor,

a first gain controller for controlling an amplitude of an input signalwith the first gain factor to supply a gain controlled signal to theprocessing circuit,

a compensation circuit for determining a second gain factor based on thefirst gain factor and input parameters defining a time variation of thesecond gain factor, and

a second gain controller for receiving an output signal of theprocessing circuit and the second gain factor to obtain a compensatedoutput signal being substantially compensated for an amplitude change ofthe gain controlled signal due to a change of the first gain factor.

The device with the automatic gain control circuit in accordance withthe invention controls an amplitude of the input signal with a firstgain factor to supply a gain controlled signal. The processing circuitprocesses the gain controlled signal into a processed signal. A secondgain controller controls a gain of the processed signal with a secondgain factor to obtain a compensated output signal which is substantiallycompensated for an amplitude change of the gain controlled signal due toa change of the first gain factor. The second gain factor is based onthe first gain factor and input parameters which define a time variationof the second gain factor. Thus, when, at a particular instant, thefirst gain factor is changed, the second gain factor is adapted in sucha way that the amplitude of the compensated output signal issubstantially constant of course only if the input signal does notchange during the transition period. In more general, the compensatedoutput signal is compensated such that it better follows the inputsignal and thus is less disturbed by the variation of the first gainfactor. This is especially important in audio applications. Anydisturbance, even if temporarily only, of the amplitude of thecompensated output signal will result in audible distortion of thesignal. The first gain factor is supplied both to the automatic gaincontrol circuit to change the amplitude of the input signal, and to thecompensation circuit to indicate the instant and/or amount of the changeof amplitude of the input signal.

The prior art U.S. Pat. No. 5,389,927 controls the analog signalamplitude in factors of two. If the digital signal is controlled infactors of two in the opposite direction of the amplitude change of thecontrolled analog signal, the difference between the analog signal andthe digital signal is reasonably small during the amplitude adaptations.However, the waveform of the digital signal temporarily deviates fromthe amplitude of the analog input signal when the amplitude of thecontrolled analog signal is changed. This causes an audible distortionevery time the step change of the amplitude of the controlled analogsignal is required. This audible distortion has to be filtered out whichdeteriorates the audio quality.

In an embodiment in accordance with invention, the processing circuitcomprises an analog to digital converter ADC. The device with theautomatic gain control circuit in accordance with the invention controlsan amplitude of the analog input signal with a first gain factor tosupply a gain controlled analog signal. The first gain factor isdetermined such that the current signal amplitude of the digital signaldoes not exceed the input range of the ADC. The ADC converts the gaincontrolled analog signal into a digital signal. A second gain controllercontrols a gain of the digital signal with a second gain factor toobtain a compensated digital signal which is substantially compensatedfor an amplitude change of the gain controlled analog signal due to achange of the first gain factor. The second gain factor is based on thefirst gain factor and input parameters which define a time variation ofthe second gain factor. Thus, the compensated digital signal iscompensated such that it better follows the analog input signal and thusis less disturbed by the variation of the first gain factor.

With the current signal amplitude of the digital signal is meant themaximum value the digital signal has or is expected to have. The bits ofthe digital signal word may be generated by the analog to digitalconverter directly in parallel, it is also possible that the analog todigital converter supplies the bits of the word serially.

In an embodiment in accordance with the invention, the gain controlprovides an input signal which fits within the operating range of theADC and thus prevents that at a too large amplitude of the analog inputsignal will be clipped by the analog to digital conversion, or that alarge part of the range of the ADC is not used.

In an embodiment in accordance with the invention, the first gain factoris adapted in steps, this is simpler than to cater for a continuouslyvariable first gain factor.

In an embodiment in accordance with the invention, the first gain factoris changed in steps which are a power of two. This allows a change ofthe digital amplitude by bit-shifting, which is very simple.

In an embodiment in accordance with the invention, a delay circuitdelays a start instant of the controlling of the amplitude of the outputsignal of the processing circuit. When the first gain factor is changed,the analog gain is adapted immediately. The second gain should howevernot be adapted immediately. It takes some time before the adaptation ofthe analog gain is noticeable in the output signal of the processingcircuit. This delay is caused by a processing time of the processingcircuit between the gain controlled signal and the compensated digitalsignal. Thus, the second gain factor should start changing after thisdelay. If the processing circuit comprises an ADC, the second gainfactor is also referred to as the digital gain factor.

In an embodiment in accordance with the invention, the compensationcircuit comprises a waveform generation circuit which generates awaveform determining the time variation of the second gain factor. Ifthe first gain factor is changed with a step, the amplitude of the gaincontrolled signal will change with a step. However, the amplitude of theoutput signal of the processing circuit will not vary stepwise. Theprocessing circuit (which may comprise an ADC and, optionally, otherdigital circuits such as digital filters) cause the step variation ofthe gain controlled signal to become smeared out in time, for exampledue to bandwidth limitations. Thus, if an amplitude of the compensatedsignal is required which is less disturbed by the step variation of thegain controlled signal, the second gain should vary in time inaccordance with a well defined waveform to compensate the smeared-outresponse.

In an embodiment in accordance with the invention, the waveformgenerating circuit comprises a bandwidth limitation circuit to obtainthe smeared-out change of the second gain factor corresponding to thesmear out effect of the processing circuit. It is also possible toapproximate or obtain the same behavior by using a linear interpolation,or even better a higher order interpolation, or by using a table look-upor a line drawing algorithm.

In an embodiment in accordance with the invention, a static error iscompensated for. If the first gain factor indicates that the amplitudeof the analog signal should change a predetermined amount, actually aslight deviation from this predetermined amount might occur. It is notsufficient to compensate the amplitude of the output signal of theprocessing circuit with exactly the same predetermined amount. After thetransition period, when the delay and the waveform of the second gainfactor are not important anymore, still a difference is present betweenthe amplitude of the compensated signal and the original input signal.This difference is compensated for by the level adaptation circuit.

In an embodiment in accordance with the invention, a well known singlebit sigma-delta analog to digital converter is used. Such an analog todigital converter is simple. A further advantage is that the gaincompensation operates on a single-bit signal instead of a multi-bitsignal thus removing the need for an explicit multiplication.

In an embodiment in accordance with the invention, the digital gain iscontrolled at the ADC directly. An example of a suitable ADC is an ADCwith a possibility to control its reference.

In an embodiment in accordance with the invention, the digital gain (thesecond gain factor) is controlled by a digital gain controller (thesecond gain controller) which processes the digital signal (theprocessed signal) supplied by the ADC. The ADC may now be of any kind.

In an embodiment in accordance with the invention, the processingcircuit may comprise further digital processing (for example a digitalfilter). The gain compensation is obtained by controlling the amplitudeof the processed digital signal supplied by the digital processingcircuit.

In an embodiment in accordance with the invention, both the gain of thedigital signal supplied by the ADC and the gain of the processed digitalsignal supplied by the digital processing circuit are controlled.

In an embodiment in accordance with the invention, an automaticcalibration circuit performs during a test period, repeatedly the nextoperations:

generating a reference signal being supplied as the input signal,

adapting the first gain factor with a predetermined amount,

providing a first set of input parameters,

checking whether a change of amplitude occurs of the compensated outputsignal, and

adapting at least one of the input parameters, until substantially nochange of amplitude occurs of the compensated output signal, and

finally storing the input parameters determined, for use during normaloperation.

These and other aspects of the invention are apparent from and will beelucidated with reference to the embodiments described by way of examplein the following description and with reference to the accompanyingdrawings, in which

FIG. 1 shows a simple gain compensation circuit,

FIG. 2 shows signals for elucidating the operation of the gaincompensation circuit shown in FIG. 1,

FIG. 3 shows a block diagram of the gain compensation circuit inaccordance with an embodiment of the invention,

FIG. 4 shows signals for elucidating the operation of the gaincompensation circuit shown in FIG. 3,

FIG. 5 shows a block diagram of the gain compensation circuit of anembodiment in accordance with the invention,

FIG. 6 shows a block diagram of the gain compensation circuit of anembodiment in accordance with the invention,

FIG. 7 shows a block diagram of the gain compensation circuit of anembodiment in accordance with the invention,

FIG. 8 shows an embodiment in accordance with the invention of a digitalgain controller, and

FIG. 9 shows an embodiment in accordance with the invention of anautomatic calibration circuit.

In the Figures, elements which correspond to elements describedpreviously have the same reference numerals.

FIG. 1 shows a simple gain compensation circuit. A gain circuit B3receives a gain control signal referred to as gain factor g, an analoginput signal S1 which has a certain dynamic range and bandwidth andsupplies a gain controlled analog signal S3 to the analog to digitalconverter B1. The gain circuit B3 usually is an attenuating circuit. Theattenuating circuit may comprise a number of attenuators (indicated by2⁰, 2⁻¹, 2^(−n)) which attenuate the analog input signal S1 with factorswhich are powers of the number 2. It is possible to use other factors. Amultiplexer M1 selects the attenuator output signal(s) fitting the gainfactor g. The ADC B1 converts the gain controlled analog input signal S3into a digital signal S4.

A detection circuit B2 continuously checks the current signal level ofthe digital signal S4 and compares this level to the maximum allowableinput-level of the ADC B1. If the level of the digital signal S4approaches the maximum allowable level, the detection circuit B2 adaptsthe gain factor g to obtain a same attenuation factor g of the gaincircuit B3. The scaling of the ADC B1 output signal, which is thedigital signal S4, introduced by the attenuating circuit B3 is latercompensated by a digital gain controller B10 which amplifies the digitalsignal S4 by the same factor g to obtain a digital output signal S2which has an amplitude which is as constant as possible.

For an efficient implementation of the digital gain controller B10,often the attenuating circuit B3 comprises the above mentioned set offixed attenuation factors which are powers of 2, which thus gives riseto attenuation in multiples of 6 dB. The digital gain controller B10increases the amplitude of the digital signal S4 in steps of 6 dB bysimply shifting the bits of the digital word by one bit. In fact, moregenerally, the attenuation-factor g determines an attenuation-factor(the powers of 2 indicated in the digital gain controller B10) selection(by the multiplexer M2) in the digital gain controller B10.

The switching of the attenuation factor g of the attenuating circuit B3happens almost instantaneously, resulting in a step-wise amplitudechange in the gain controlled analog signal S3. Due to the bandwidthlimitation inherently present in the system, for example, due of the ADCB1, this step is spread out, and after some delay TD (see FIG. 2) thestep results in a relatively slow transient TR of the digital signal S4.In addition to the delay TD and the transient TR, there is asetting-dependent deviation E from the ideal attenuation due toprocess-spread and non-idealities in the analog design. In this simplegain compensation circuit, the attenuation is compensated by a step andthe digital output signal S2 is temporarily distorted. This isillustrated with respect to FIG. 2.

Depending on the application, all these distortions result in unwantedand noticeable artifacts. For example, in case of AM-reception, thesedistortions give rise to a click-noise in the output audio signal whicheither has to be filtered out or muted, and thus leads to inferior audioquality. This effect becomes worse if the AGC switches periodically orwith a certain periodicity.

FIG. 2 shows signals for elucidating the operation of the simple gaincompensation circuit. FIG. 2A shows the gain factor g which increasesalmost stepwise at instant t1. This indicates to the gain circuit B3that the amplitude of the gain controlled analog signal S3 shoulddecrease a predetermined amount, and to the digital gain controller B10to increase the amplitude of the digital signal S4 with the samepredetermined amount. FIG. 2B shows the stepwise decrease of theamplitude of the gain controlled analog signal S3. FIG. 2C shows thechange of the digital signal S4 in response to the step of the amplitudeof the gain controlled analog signal S3. The amplitude of the digitalsignal S4 starts decreasing at an instant t2 which is a delay time TDlater than instant t1 at which the gain controlled analog signal S3decreases. During a transition period TR (also referred to as thetransition TR), the amplitude of the digital signal S4 decreases to itsfinal level. The final level which is reached at instant t3 may have anoffset or error E with respect to the expected level. FIG. 2D shows thecompensated digital signal S2. The gain factor g of FIG. 2A corrects thedigital signal S4 by enlarging the gain of the digital gain controllerB10 at the instant t1 at which the digital signal 84 is not changed dueto the stepwise change of the gain controlled analog signal S3.Consequently, the amplitude of the compensated digital signal S2 is toolarge. At instant t2 the too large amplitude of the compensated digitalsignal S2 starts decreasing due to the decreasing amplitude of thedigital signal S4. After instant t3, the desired level DL is reached,only the error B will still be present.

Due to the imperfect compensation, a much too high amplitude of thecompensated digital signal occurs from instant t1 to instant t3. Thisdistortion will be audible in audio systems. A much too low amplitude ofthe compensated digital signal will occur if the step occurs in theother direction.

FIG. 3 shows a block diagram of the gain compensation circuit inaccordance with an embodiment of the invention.

The gain circuit B3 receives a gain control signal referred to as gainfactor g, and an analog input signal S1, and supplies a gain controlledanalog signal S3 to the analog to digital converter B1. The gain circuitB3 may be identical to the gain circuit B3 described with respect toFIG. 1. The ADC B1 converts the gain controlled analog input signal S3into a digital signal S4.

A detection circuit B2 continuously checks the current signal level ofthe digital signal S4 and compares this level to the maximum allowableinput-level of the ADC B1. If the level of the digital signal S4approaches the maximum allowable level, the detection circuit B2 adaptsthe gain factor g to obtain a same attenuation factor g of theattenuating circuit B3. The scaling of the ADC B1 output signal, whichis the digital signal S4, introduced by the attenuating circuit B3 islater compensated by a digital gain controller B10. A compensationcircuit B5 determines a digital gain factor dg based on both the gainfactor g which comprising information on when the gain factor is changedand by how much and on parameters DL, TR, DV which determine thevariation in time of the digital gain factor dg. The digital gaincontroller B10 controls the gain of the digital signal S4 with a factordetermined by the digital gain factor dg to obtain a digital outputsignal S2 which has an amplitude which is substantially constant or moreprecisely defined if the input signal is varying: an amplitude which issubstantially undisturbed.

The main idea of the compensation circuit in accordance with a preferredembodiment of the invention is to implement a gain compensation whichsubstantially perfectly compensates for the non-idealities describedwith respect to the simple compensation as elucidated with respect toFIGS. I and 2. In principle the substantially perfect compensation isobtained by means of time-varying the gain of the digital gaincontroller B10 in such a way that the artifacts in the compensateddigital signal S2 are substantially removed.

The compensation circuit B5 generates a digital gain factor dg which iscomplementary to all the distortions seen at the point in the processingchain where the gain compensation is performed. This digital gain factordg is used as a compensation signal for the digital gain controller B10.In principle, in a preferred optimal compensation scheme, the digitalgain factor dg is determined based on the gain factor g, the delay TD,the transition characteristics of the transition TR and the error E. Thecompensation circuit B5 thus generates a digital gain dg with aprogrammable delay, start-gain, end-gain and transition characteristics.The digital gain in accordance with the invention thus is not just astep-wise compensation which occurs coincident with the change of thegain factor, but has at least either a delay, a changing value, or onstatic error compensation component.

The digital gain controller B10 may be identical to the one describedwith respect to FIG. 1.

FIG. 4 shows signals elucidating the operation of the gain compensationcircuit shown in FIG. 3. FIG. 4A shows the gain factor g which switchesfrom attenuation factor gk to gi at instant t1. The gain controlledanalog signal S3 which is the ADC B1 input signal almost immediatelyresponds to the new setting of the attenuating circuit B3 as is shown inFIG. 4B. This new setting deviates with a setting depending deviation Efrom the ideal attenuation. The analog to digital conversion by the ADCB1 introduces a processing delay TD. The gain compensation circuit B5generates the digital gain factor dg as shown in FIG. 4D. The digitalgain factor dg starts increasing at instant t2 which is the delay timeTD later than the instant t1. The digital gain factor dg increases untilthe instant t3 along a curve which is complement to the correspondingcurve of the amplitude error of the digital signal S4 if notcompensated. After instant t3, the digital gain factor dg has a valuesuitable to compensate for the error E. The distortions aresubstantially perfectly compensated in the compensated digital signal S2as shown in FIG. 4E. It is not required that all the aspects arecompensated. The compensated digital signal S4 has a less distortedamplitude than in the prior art even when the error E is not or notfully compensated. It is also not required to perfectly compensateduring the transition period. A rough estimation of the optimal curveduring the transition period will improve the behavior of thecompensation circuit over the prior art. An improvement over the priorart is obtained also when at least one of the effects of delay time TD,the transition period TR, or the error E is compensated to at least someextend.

The shape of the curve of the digital gain dg during the transitionperiod TD may be obtained by linear interpolation of two or morevalue/time pairs which preferably are obtained from a memory (notshown). A better accuracy may be reached by using a higher orderinterpolation. Alternatively, well known methods like table look-up orline-drawing algorithms can be used depending on a trade-off betweenaccuracy and effort.

Preferably, all the parameters determining the variation of the digitalgain factor dg during the transition period TR, the duration of thedelay period TD, and the setting-dependent deviation or error E are userprogrammable.

FIG. 5 shows a block diagram of an embodiment in accordance with theinvention of the gain compensation circuit.

The gain circuit B3 receives a gain control signal referred to as gainfactor g, an analog input signal S1 and supplies a gain controlledanalog signal S3 to the analog to digital converter B1. The ADC B1further comprises an input to receive the digital gain factor dg andconverts the gain controlled analog input signal S3 into a gaincompensated digital signal S2. A detection circuit B2 continuouslychecks the current signal amplitude of the compensated digital signal S2and/or the gain controlled analog signal S3 to determine the gain factorg. A compensation circuit B5 determines the digital gain factor dg basedon the gain factor g, and the parameters for the duration of the delayperiod TD, for the shape of the gain variation during the transitionperiod TR, and the error E.

This digital gain control in the ADC B1 is in particular relevant forADC's of which the reference can be controlled.

FIG. 6 shows a block diagram of an embodiment in accordance with theinvention of the gain compensation circuit.

The controllable variable gain circuit B3 receives the gain factor g,the analog input signal S1 and supplies the gain controlled analogsignal S3 to the analog to digital converter B1 which converts the gaincontrolled analog signal S3 into a digital signal S4. A detectioncircuit B2 continuously checks the current signal amplitude of thedigital signal S4 and/or the gain controlled analog signal S3 todetermine the gain factor g. A digital processing circuit B11 receivesthe digital signal S4 and supplies the processed digital signal S5 tothe digital gain controller B10 to obtain the compensated digital signalS2. The compensation circuit B5 determines the digital gain factor dgbased on the gain factor g, and the parameters for the duration of thedelay period TD, for the shape of the gain variation during thetransition period TR, the error E, and the processing in the processingcircuit B11. The digital gain factor dg is supplied to the digital gaincontroller B10 to control the amplitude of the processed digital signalS5. The digital processing circuit B11 may perform decimation filtering.

The compensation of the gain variation by the gain circuit B3 in theanalog domain is compensated in the digital domain behind the digitalprocessing circuit B11. This has the advantage that if the digitalprocessing circuit B11 comprises a sample rate down-converter, or adecimation filter that the compensation is performed on a signal with alower sample rate.

FIG. 7 shows a block diagram of an embodiment in accordance with theinvention of the gain compensation circuit.

The controllable variable gain circuit B3 receives the gain factor g,the analog input signal S1 and supplies the gain controlled analogsignal S3 to the analog to digital converter B1 which converts the gaincontrolled analog input signal S3 into a digital signal S4. A detectioncircuit B2 continuously checks the current signal amplitude of thedigital signal S4 and/or the gain controlled analog signal S3 todetermine the gain factor g. A digital gain controller B12 receives thedigital signal S4 to supply an intermediate compensated digital signalS6. A digital processing circuit B11 receives the intermediatecompensated digital signal S6 and supplies the processed digital signalS5 to the digital gain controller B10 to obtain the compensated digitalsignal S2. A compensation circuit B14 a determines the digital gainfactor dga based on the gain factor g, and the parameters for theduration of the delay period TD, for the shape of the gain variationduring the transition period TR, and the error E. The digital gainfactor dga is supplied to the digital gain controller B12 to control theamplitude of the digital signal S4. A compensation circuit B14 bdetermines the digital gain factor dgb based on the gain factor g, andthe parameters for the duration of the delay period TD, for the shape ofthe gain variation during the transition period TR, the error E, and theprocessing of the processing circuit B11. The digital gain factor dgb issupplied to the digital amplifier B10 to control the gain of theprocessed digital signal S5.

Now the compensation of the of the gain variation by the gain circuit B3in the analog domain is compensated in the digital domain partlydirectly behind the ADC B1 and partly behind the digital processingcircuit B11. This has the advantage that if the digital processingcircuit B11 comprises a sample rate down-converter, or a decimationfilter that the compensation is performed on a signal with a lowersample rate.

FIG. 8 shows an embodiment in accordance with the invention of acompensation circuit.

The compensation circuit B5 or B14 b, B14 b comprises a delay circuitB6, a waveform generating circuit B7, a level adaptation circuit B8 anda combining circuit B9.

The delay circuit receives B6 the gain factor g and a delay parameter DLto supply the delay time TD. The delay time TD indicates an instant adelay time TD later than the instant at which the gain factor g changes.The duration of the delay time TD is determined by the delay parameterDL. The delay parameter may be stored in memory.

The waveform generating circuit B7 receives the gain factor g and atleast one waveform parameter WP defining the waveform information WFaccording which the digital gain dg has to vary during the transitionperiod TR. The waveform generating circuit B7 may receive timinginformation TI from the delay circuit B6 which at least indicates thestart of the transition period. The waveform parameter WP may comprisethe timing information on the duration of the transition period and alsoon the start of the transition period with respect to the instant thegain factor g changes. The waveform parameter WP further comprises oneor more values determining the desired waveform information WF. The gainfactor g provides information on the required amount the digital gain dgshould vary, and on the instant the gain in the analog domain ischanged. However, this timing instant may not be used as it may bepresent in the timing information TI. The waveform generating circuit B7may receive information on a correction required to compensate for theinfluence of a processing circuit B11 if present.

The level adaptation circuit B8 receives a delta gain factor DV and thegain factor g to determine the amount the digital gain dg has to change,and on the instant the gain in the analog domain is changed. The deltagain factor DV indicates the value for the offset or error information Erequired to obtain a perfect compensation after the transition periodTR. The timing information (obtained from the gain factor g or from thedelay circuit B6) may be used to activate this compensation during orafter the transition period TR.

The combining circuit B9 combines the delay parameter DL, the waveforminformation WF and the error information E to obtain the time-varyingdigital gain or digital gain factor dg.

FIG. 9 shows an embodiment in accordance with the invention of anautomatic calibration circuit. The circuit shown in FIG. 9 is based onthe circuit shown in FIG. 3. An automatic calibration circuit B13 and aswitch SW are added. The automatic calibration circuit B13 receives thecompensated digital signal S2, and supplies: a switch control signal SWSto the switch SW, the parameters DL, TR, and OV to the compensationcircuit B5, and a control signal AG to the gain circuit B3 and thecompensation circuit BS.

During a calibration period, the automatic calibration circuit B13 firstsets the parameters DL, TR and OV. Secondly, the automatic calibrationcircuit B13 supplies a reference signal RS with a predetermined level asthe analog signal S1 to the controllable variable gain circuit B3because the switch SW is in the position shown. Then, the automaticcalibration circuit B13 provides the information AG to the gain circuitB3 and the compensation circuit B5 to indicate the instant at which thegain of the gain circuit B3 and the digital gain controller B10 has tobe changed. Instead of supplying the information AG directly to the gaincircuit B3 and the compensation circuit B5, the information AG may alsocontrol the gain factor g. Now, the automatic calibration circuit B13evaluates the amplitude of the compensated digital signal S2.

If the amplitude of the compensated digital signal S2 is sufficientlyconstant in time, the parameters DL, TR and OV used are stored andnormal operation is resumed. During normal operation, the switch SW isin the position not shown in FIG. 9 and the automatic calibrationcircuit is inactive.

If the amplitude of the compensated digital signal S2 is notsufficiently constant in time, the automatic calibration circuit B13varies one or more of the parameters DL, TR and OV and restarts acalibration cycle. The automatic calibration circuit B13 repeats thecalibration cycle as often as required to obtain a substantiallyconstant compensated digital signal S2 in response to a change of thegain factor g. At the end of the last calibration cycle the optimalparameters DL, TR and OV found are stored for use during the normaloperation phase.

Many strategies can be used to find the optimal parameters DL, TR andOV. For example, by determining at which instant the compensated digitalsignal deviates from the required level. For example, when a deviationoccurs near to the instant the gain factor g is changed, the parameterDL should be adapted to get a longer delay time TD, if a long time afterthis instant an error is present, the parameter OV should be changed tolower the error E. The remaining error can be minimized by sampling thedeviation during the transition period and by using the sampled valuesin the parameter TR.

The general context of this invention is the technique of automatic gaincontrol in combination with analog to digital converters used in variouskinds of applications, e.g. radio receivers, wire-line communication,data transceivers etc.

An example of an implementation is elucidated in the now following. Thecompensation circuit or the corresponding compensation method describedhas been implemented in hardware on a test-chip in the context of adigitally implemented analog broadcast AM/FM radio receiver forcar-radio applications. For a hardware-efficient solution a single-bitsigma-delta ADC is used. The test-chip comprises a set of 4 attenuatorsettings. The digital gain compensation is performed as early aspossible in the system, which is immediately on the bit-stream of theADC. This has the advantage of low hardware effort since the gaincompensation operates on a single signal-bit instead of a multi-bit-busthus removing the need for explicit multiplication. To compensate duringthe transient period TR, linear interpolation showed to provide goodperformance in that the remaining disturbances were not audible. Theuser programmable parameters DL, TR and OV are the duration of the delayperiod TD, the slope of the linear interpolated waveform of the digitalgain during the transition period TR, and four attenuator settingdependent gain deviations E, respectively.

This method of compensation can be used, for example, in the followingapplications: in general applications which use an ADC and steppedAGC's, in integrated circuits for e.g. car-radio, cellular phones,portable radio etc. RF-, LF-, and baseband-processing, and in audio(HiFi-) equipment. The method of compensation is also useful in systemswithout an ADC. Usually, processing circuits are used which have alimited dynamic range. Often the dynamic range is limited by the powersupply voltages applied. In particular if circuits are integrated in anintegrated circuit, the dynamic range of these circuits may be quitelimited due to relatively low supply voltages. The amplitude of theinput signal of such processing circuits is controlled by a first gaincontrol circuit preceding the processing circuit. The effect of thefirst gain control circuit is substantially compensated by providing asecond gain control circuit operating on the output signal of theprocessing circuit to restore the amplitude of the output signal.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims.

In the claims, any reference signs placed between parentheses shall notbe construed as limiting the claim. Use of the verb “comprise” and itsconjugations does not exclude the presence of elements or steps otherthan those stated in a claim. The article “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.The invention may be implemented by means of hardware comprising severaldistinct elements, and by means of a suitably programmed computer. Inthe device claim enumerating several means, several of these means maybe embodied by one and the same item of hardware. The mere fact thatcertain measures are recited in mutually different dependent claims doesnot indicate that a combination of these measures cannot be used toadvantage.

1. A device comprising a processing circuit (B1; B1, B11) with apredetermined limited dynamic range, and an automatic gain controlcircuit comprising: a gain determining circuit (B2) for determining afirst gain factor (g), a first gain controller (B3) for controlling anamplitude of an input signal (S1) with the first gain factor (g) tosupply a gain controlled signal (S3) to the processing circuit (B1; B1,B11), a compensation circuit (B5) for determining a second gain factor(dg) based on the first gain factor (g) and input parameters (DL, TR,DV) defining a time variation of the second gain factor (dg), and asecond gain controller (B1; B10) for receiving an output signal of theprocessing circuit (B1; B1, B11) and the second gain factor (dg) toobtain a compensated output signal (S2) being substantially compensatedfor an amplitude change of the gain controlled signal (S3) due to achange of the first gain factor (g).
 2. A device as claimed in claim 1,wherein the processing circuit (B1; B1, B11) comprises an analog todigital converter (B1) for converting the gain controlled signal (S3)into a digital signal (S4; S2), the output signal of the processingcircuit (B1; B1, B11) being a digital signal (S4), and the compensatedoutput signal (S2) being a compensated digital signal (S2).
 3. A deviceas claimed in claim 2, wherein the gain determining circuit (B2) hasinputs for receiving the gain controlled signal (S3) and/or the digitalsignal (S4) and an output for supplying the first gain factor (g), thefirst gain factor (g) being determined to obtain the amplitude of thegain controlled signal (S3) fitting within an operating range of theanalog to digital converter (B1).
 4. A device as claimed in claim 3,wherein the gain determining circuit (B2) is arranged for adapting thefirst gain factor (g) in steps.
 5. A device as claimed in claim 4,wherein the steps comprise powers of the number two.
 6. A device asclaimed in claim 2, wherein the analog to digital converter (B1) is of asingle bit sigma-delta type.
 7. A device as claimed in claim 2, whereinthe analog to digital converter (B1) comprises the second gaincontroller (B1; B10) for controlling the gain of the digital signal (S4)to supply the compensated digital signal (S2).
 8. A device as claimed inclaim 2, wherein the second gain controller (B1; B10) is arranged forcontrolling the gain of the digital signal (S4) supplied by the analogto digital converter (B1).
 9. A device as claimed in claim 2, whereinthe processing circuit (B1; B1, B11) comprises a digital processingcircuit (B11) for processing the digital signal (S4) supplied by theanalog to digital converter (B1) to obtain a processed digital signal(S5), and wherein the second gain controller (B10) is arranged forcontrolling a gain of the processed digital signal (S5) with the secondgain factor (dg).
 10. A device as claimed in claim 9, further comprisinga digital gain controller (B12) being arranged between the analog todigital converter (B11) and the digital processing circuit (B11), thedigital gain controller (B12) being controlled by a further digital gainfactor (dga).
 11. A device as claimed in claim 1, wherein thecompensation circuit (B5) comprises a delay circuit (B6) for delaying astart instant of a change of the second gain factor (dg) in response tothe change of the first gain factor (g) to substantially compensate fora processing time of the processing circuit (B1; B1, B11) causing a timedelay (TD) between the gain controlled signal (S3) and the compensatedoutput signal (S2).
 12. A device as claimed in claim 1, wherein thecompensation circuit (B5) comprises a waveform generating circuit (B7)for generating a waveform (WF) of the time variation of the second gainfactor (dg).
 13. A device as claimed in claim 12, wherein the waveformgenerating circuit (B7) comprises a bandwidth limitation circuit, or alinear interpolation circuit, or a higher order interpolation circuit,or a table look up circuit, or a line drawing algorithm circuit.
 14. Adevice as claimed in claim 1, wherein the compensation circuit (B5)comprises a level adaptating circuit (B8) for generating a DC-offset ofthe second gain factor (dg) to substantially compensate for a staticlevel deviation (E) of the compensated output signal (S2).
 15. A deviceas claimed in claim 1, further comprising an automatic calibrationcircuit (B13) being arranged for, during a test period (TP), repeatedly:generating a reference signal (RS) being supplied as the input signal(S1), adapting the first gain factor (g) with a predetermined amount,providing a first set of input parameters (DL, TR, DV), checking whethera change of amplitude occurs of the compensated output signal (S2), andadapting at least one of the input parameters (DL, TR, DV), untilsubstantially no change of amplitude occurs of the compensated outputsignal (S2), and finally storing the input parameters (DL, TR, DV)determined, for use during normal operation.
 16. A method of automaticgain control in a device comprising a processing circuit (B1; B1, B11)with a predetermined limited dynamic range, the method comprising:determining (B2) a first gain factor (g), controlling (B3) an amplitudeof an input signal (S1) with the first gain factor (g) to supply a gaincontrolled signal (S3) to the processing circuit (B1; B1, B11),determining (B5) a second gain factor (dg) based on the first gainfactor (g) and input parameters (DL, TR, DV) defining a time variationof the second gain factor (dg), and controlling (B1; B10) with thesecond gain factor (dg) an output signal of the processing circuit (B1;B1, B11) to obtain a compensated output signal (S2) being substantiallycompensated for an amplitude change of the gain controlled signal (S3)due to a change of the first gain factor (g).
 17. A method of automaticgain control as claimed in claim 16, further comprising an automaticcalibration (B13) comprising, during a test period, repeatedly:generating a reference signal (RS) being supplied as the input signal(S1), adapting the first gain factor (g) with a predetermined amount,providing a first set of input parameters (DL, TR, DV), checking whethera change of amplitude occurs of the compensated output signal (S2), andadapting at least one of the input parameters (DL, TR, DV), untilsubstantially no change of amplitude occurs of the compensated outputsignal (S2), and finally storing the input parameters (DL, TR, DV)determined, for use during normal operation.
 18. An audio apparatuscomprising a processing circuit (B1; B1, B11) with a predeterminedlimited dynamic range, and an automatic gain control circuit comprising:a gain determining circuit (B2) for determining a first gain factor (g),a first gain controller (B3) for controlling an amplitude of an inputsignal (S1) with the first gain factor (g) to supply a gain controlledsignal (S3) to the processing circuit (B1; B1, B11), a compensationcircuit (B5) for determining a second gain factor (dg) based on thefirst gain factor (g) and input parameters (DL, TR, DV) defining a timevariation of the second gain factor (dg), and a second gain controller(B1; B10) for receiving an output signal of the processing circuit (B1;B1, B11) and the second gain factor (dg) to obtain a compensated outputsignal (S2) being substantially compensated for an amplitude change ofthe gain controlled signal (S3) due to a change of the first gain factor(g).